This application claims priority of Japanese Patent Application Number 2002-081042, filed Mar. 22, 2002.
1. Field of the Invention
The present invention relates to an analog/digital converter, more particularly relates to a low power consumption, high conversion accuracy, high speed operation analog/digital converter.
2. Description of the Related Art
Analog/digital converters are widely used in various fields for converting analog signals to digital signals.
There are various forms of analog/digital converters. As a high speed operation type, generally a flash type is used.
A flash type analog/digital converter converts an input voltage Vi between a top voltage VT and a bottom voltage VB to an N-bit digital signal and uses a reference voltage output circuit comprised of M number of dividing resistances R1 to RM dividing the range between the top voltage VT and the bottom voltage VB into M=2N connected in series.
(Mxe2x88x921) number of voltage division points are connected to one-side terminals (for example, negative input terminals) of (Mxe2x88x921) number of comparators C1 to CMxe2x88x921. The other terminals (for example, positive input terminals) of the comparators C1 to CMxe2x88x921 are connected in common. The input voltage Vi is applied to the common terminal.
That is, when the input voltage Vi is larger than VB+(VTxe2x88x92VB)/M and smaller than VB+2(VTxe2x88x92VB)/M, only the comparator C1 arranged at the bottommost voltage VB side is inverted. The other comparators C2 to CMxe2x88x921 maintain their non-inversion states.
In general, when the input voltage Vi is larger than VB+(VTxe2x88x92VB)xc2x7(mxe2x88x921)/M and smaller than VB+(VTxe2x88x92VB)xc2x7m/M, the comparators C1 to Cmxe2x88x921 at the bottom voltage VB side are inverted and the remaining comparators Cm to CMxe2x88x921 maintain their non-inversion state (where, m=1, 2 . . . M).
Further, the outputs of the comparators C1 to CMxe2x88x921 are connected to the encoder EN. The outputs of the (Mxe2x88x921) number of comparators are output encoded to an N-bit digital signal.
The parts of the flash-type analog/digital converter are built into an integrated circuit, but the resistance values of the M number of dividing resistances and the offsets of the (Mxe2x88x921) number of comparators vary and a drop in the conversion accuracy is unavoidable.
FIG. 2 is a view explaining the operating characteristic of a comparator. The abscissa indicates the differential voltage between an input voltage Vi applied to a positive input terminal and a divided voltage applied to the negative input terminal, while the ordinate indicates the output of the comparator.
Comparators are produced designed so as to invert in output at a differential voltage of 0V, but sometimes the inversion voltage deviates from 0V due to variations at the time of fabrication of the integrated circuit. This deviation is called xe2x80x9coffsetxe2x80x9d.
To prevent a decline in the conversion accuracy due to variation in offset, the technique is proposed of building a plurality of (for example, three) comparators into each of the comparators C1 to CMxe2x88x921 and selecting the comparator giving the smallest offset for the conversion in the inspection or calibration process.
Even if building in a plurality of comparators, there is no guarantee that there will be a comparator with an offset of 0V. There are therefore limits to the improvement of the conversion accuracy.
Therefore, to improve the conversion accuracy, it is proposed to divide each of M number of dividing resistances R1 to RM into a plurality of resistances and select the division position for supplying a reference voltage to a comparator in the inspection or calibration process to minimize the offset of that comparator (see Japanese Unexamined Patent Publication (Kokai) No. 10-65542).
FIG. 3 is a view of the configuration of an analog/digital converter of the related art to which the above technology is applied. The dividing resistances R1 and RM are divided into two resistances, while the dividing resistances R2 to RMxe2x88x921 are divided into three resistances. Further, three adjoining resistances are connected through a switch to one of the terminals of each of the comparators C1 to CMxe2x88x921.
On the other hand, M+1 number of reference voltages including the top voltage VT and bottom voltage VB are fed back through the switches to the input voltage terminals. Further, the output of the encoder is led to a switch control circuit SC. The switch control circuit SC controls the operation of the switches arranged between the dividing resistances and comparators and the switches for feeding back the dividing resistances to the input voltage terminals.
Further, at the calibration mode, the circuit feeds back one of the divided voltages to the input voltage terminals and selects the dividing resistances for connection to the comparators so that the corresponding comparators invert at a predetermined standard reference voltage.
Summarizing the problems to be solved by the invention, the following problems occur in an analog/digital converter of the above configuration:
(1) It is necessary to select the connection point for each comparator, so when the number of bits of the analog/digital converter is increased, time is taken for selection of the connection points.
Further, it is necessary to take into consideration the time from when switching the switches to when the outputs of the comparators stabilize, so the time required for selection of the connection points becomes further longer.
(2) If reducing the power supply voltage for reducing the power consumption of the analog/digital converter, sometimes the connection points cannot be determined.
That is, when reducing the voltage, the differential voltage between the top voltage VT and the bottom voltage VB becomes small, so the dynamic range of the input voltage also becomes small. As opposed to this, the offsets of the comparators are determined by the method of production of the integrated circuit, so the offsets become relatively large.
In the analog/digital converter of the above configuration, however, since the connection points have to be determined from limited ranges centered around standard connection points (in this embodiment, the standard connection division point and two division points above and below the same), when the offsets are large, sometimes the offsets cannot be corrected even when changing the connection points.
For example, if the differential voltage between the top voltage VT and the bottom voltage VB is Vd and the number of bits of the digital output is N, the voltage corresponding to the least significant bit (LSB) becomes Vd/2N.
When forming the comparators in an integrated circuit, the offsets are liable to become as high as 40 mV. In the analog/digital converter of the above configuration, however, the adjustable range of offset becomes 1 LSB, that is, 40 mV, so the power supply voltage must become more than 40xc2x72N mV.
For example, when N=6, the power supply voltage has to be more than 40xc2x764=2560 mV=2.56V. An analog/digital converter having a power supply voltage of 1V cannot be made.
(3) Further, since the analog/digital converter of the above configuration controls the connection and division points based on the results of encoding of the outputs of the comparators by the encoder EN, it is not possible to detect scrambling of the operating sequence of the comparators.
That is, in a flash-type analog/digital converter of the related art, the comparators have to sequentially invert along with a change in the input voltage, but sometimes the inversion sequence becomes scrambled due to the offset. For example, when the input voltage gradually rises, the comparators should invert in the sequence of Cmxe2x88x921CmCm+1, but when the offset of the comparator Cm is large, sometimes the comparator Cm will not invert and the other comparators will invert in the sequence of Cmxe2x88x921 to Cm+1.
In the analog/digital converter of the above configuration, however, sometimes it is not possible to correctly recognize scrambling of the inversion sequence since the outputs of the comparators are encoded and the connection and division points are switched.
An object of the present invention is to provide a low power consumption, high conversion accuracy, and high speed operation analog/digital converter.
According to the present invention, there is provided an analog/digital converter for converting an analog voltage to N bits of a digital signal, comprising (2Nxe2x88x921) number of comparing means; a reference voltage outputting means for dividing a differential voltage of a top voltage and bottom voltage into at least (2N) number of sections and outputting at least (2N+1) number of reference voltages including said top voltage and bottom voltage; a calibration voltage outputting means for outputting a ramp-like voltage to one-side input terminals of said (2Nxe2x88x921) number of comparing means at a calibration mode; a calibrating means for selecting a voltage to be supplied to the other input terminal of one predetermined comparing means making that comparing means invert from the at least (2N+1) number of reference voltages output from said reference voltage outputting means when the output voltage of said calibration voltage outputting means reaches each of the (2Nxe2x88x921) number of reference inverted voltages set in the design at a calibration mode; and a reference voltage applying means for applying a reference voltage selected by said calibrating means to the other terminals of the above (2Nxe2x88x921) number of comparing means.
In the present invention, a reference voltage making the offset of the calibrating means less than a predetermined threshold by application of a ramp-like calibration voltage to the comparing means is selected.
Preferably, said calibrating means comprises a reference voltage selecting means for selecting one predetermined voltage from the at least (2N+1) number of reference voltages output from said reference voltage outputting means and applying it to the other terminals of said (2Nxe2x88x921) number of comparing means; a calibration voltage range detecting means for detecting if the output voltage of said calibration voltage outputting means is in a predetermined range from said bottom voltage to said top voltage; an inversion time counting means for counting the time (inversion time) from when the output voltage of said calibration voltage outputting means becomes more than said bottom voltage to when the outputs of said (2Nxe2x88x921) number of comparing means invert when inversion of said (2Nxe2x88x921) number of comparing means is detected by said calibration voltage range detecting means while the output voltage of said calibration voltage detecting means is in said predetermined range; a converting means for converting an inversion time counted by said inversion time counting means to an inversion voltage after the fact that the output voltage of said calibration voltage outputting means has become more than said top voltage is detected by said calibration voltage range detecting means; and a reference voltage reselecting means for reselecting a voltage to be applied to the other terminals of said (2Nxe2x88x921) number of comparing means from the at least (2N+1) reference voltages of said reference voltage outputting means when a differential voltage of the inversion voltage calculated by said converting means and the reference voltage selected by said reference voltage selecting means and applied to the other terminals of said (2Nxe2x88x921) number of comparing means is a predetermined threshold voltage or more.
In the present invention, in the state with a predetermined reference voltage applied to the other terminals of the comparing means, a ramp-like calibration voltage is applied, the inversion times of the comparing means are counted, and the reference voltage to be applied to the other terminals of the comparing means is reselected based on the results of the counting.
More preferably, said reference voltage outputting means outputs a voltage obtained by dividing the differential voltage of said top voltage and said bottom voltage by a predetermined factor of at least (2N).
In the present invention, the output voltage of the reference voltage output means is set so that the conversion characteristic of the analog/digital converter becomes a predetermined characteristic.
Alternatively, said reference voltage outputting means equally divides the differential voltage of said top reference voltage and said bottom reference voltage into at least (2N).
In the present invention, the output voltage of the reference voltage outputting means is set so that the conversion characteristic of the analog/digital converter becomes linear.
More preferably, said calibration voltage range detecting means is formed in physical dimensions larger than the physical dimensions of said (2Nxe2x88x921) comparing means in an integrated circuit.
In the present invention, the comparator used for the calibration voltage range detecting means is formed larger than the comparators of the comparing means.
Alternatively, said calibration voltage range detecting means is comprised of a plurality of second comparing means formed in the same physical dimensions as said (2Nxe2x88x921) number of comparing means in an integrated circuit and receiving as input the same input signals and a majority value computing means for computing a majority value of outputs of the plurality of second comparing means.
In the present invention, the calibration voltage range detecting means is determined by the majority value of a plurality of comparators formed to the same size as the comparators of the comparing means.